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Hardware
IP Cores
ISE
Lab has also gained recognition for the design and development
of standards-conforming conventional and public key encryption.
All popular cryptographic algorithms have been implemented as
IP Cores including:
1. Advanced Encryption Standard (AES)
2. Data Encryption Standard (DES)
3. Triple DES (TDES)
4. ElGamal
5. RSA cryptosystems
6. Digital Signature Standard (DSA)
7. Diffie-Hellman key exchange
8. Secure Hash Standards (SHA-1, SHA-256/384/512),
9. Internet MD2/MD4/MD5 message digests,
10. IEEE 32-bit CRC
These
cores are delivered in fully synthesizable RTL VHDL code as well
as related synthesis scripts and other necessary materials. We
have optimized the cores for ASICs and FPGAs respectively, using
techniques and figures of merit specific for these technologies.
The implemented algorithm is fully compatible with the most recent
version of the draft Federal Information Processing Standard (FIPS)
published by NIST and other international standards.
These
designs are flexible enough to be targeted for different application
scenarios. It can be used either as a standalone ASIC chip or
as an IP core embedded into System-on-Chip (SoC) design. Especially,
an on-chip AES core offers highly improved security level and
throughput by closely coupling data generation and encryption.
(In other words, data stream is encrypted before it goes out of
chip.) Meanwhile, these cores support multiple delivering forms
that are suitable for today's typical SoC design styles and flows.
Thus, it has extensive potential for future network and telecommunication
SoCs.
They
can be integrated into Smart Cards, Personal Trusted Device (e.g.
PDA and cellular phone), secureID token etc. Typical applications
include VPN, IPSec, SSL, and it is suitable for use with the IEEE
802.11 Standard (Wireless LAN).
For
more information or purchase, please contact info@iselab.com.
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